The disclosure relates generally to electromagnetic sensing and sensors and also relates to low energy electromagnetic input conditions as well as low energy electromagnetic throughput conditions. The disclosure relates more particularly, but not necessarily entirely, to optimizing the tolerances desired for using a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates and associated systems, methods and features.
There has been a popularization of the number of electronic devices that utilize and include the use of imaging/camera technology in general. For example, smartphones, tablet computers, and other handheld computing devices all include and utilize imaging/camera technology. The use of imaging/camera technology is not limited to the consumer electronics industry. Various other fields of use also utilize imaging/camera technology, including various industrial applications, medical applications, home and business security/surveillance applications, and many more. In fact, imaging/camera technology is utilized in nearly all industries.
Due to such popularization, the demand for smaller and smaller high definition imaging sensors has increased dramatically in the marketplace. High resolution and high definition means that more data and must be moved in a relatively smaller space. The device, system and methods of the disclosure may be utilized in any imaging application where size and form factor are considerations. Several different types of imaging sensors may be utilized by the disclosure, such as a charged-couple device (CCD), or a complementary metal-oxide semiconductor (CMOS), or any other image sensor currently known or that may become known in the future.
CMOS image sensors typically mount the entire pixel array and related circuitry, such as analog-digital converters and/or amplifiers, on a single chip. The size limitations of a CMOS image sensor often require that increasing more data is being moved within increasingly smaller confines. The contact pads between circuits can be manufactured smaller and smaller between the sensor and other important functions, such as signal processing, due to the number of considerations that must be accounted for in the design and manufacture of a CMOS image sensor. Thus, for example, increasing the pixel array area may come with a trade-off in other areas, such as A/D conversion or other signal processing functions, because of the decreased area in which the related circuitry may occupy.
The disclosure optimizes and maximizes the pixel array without sacrificing quality of the signal processing by optimizing and maximizing the pixel array on a first substrate and stacking related circuitry on subsequent substrates. The disclosure utilizes advancements in back-side illumination and other areas to take advantage of optimizing the area of the pixel array on a substrate. The stacking scheme and structure allow highly functional, large-scale circuits to be utilized while maintaining a small chip size.
The features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by the practice of the disclosure without undue experimentation. The features and advantages of the disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.